Samsung VS TSMC

These days, the media overly emphasized the competitive structure of Samsung Electronics and TSMC, and even described it as if it were a national war, saying that it was fighting'the whole of Taiwan'. It seems to have been trying to create public opinion that the jail sentence should be avoided before the ruling Lee Jae-yong. TSMC invests 30 trillion won, but Samsung is lagging behind. Eventually, after being arrested, these knights suddenly disappeared. Instead, there are articles stating that Samsung is investing at least tens of trillion won in the United States. Of course, it is sourced from foreign media such as Bloomberg and WSJ.

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1. The sales ratio of the old process is gradually decreasing, and the key is the ultra-fine process.

https://www.trendforce.com/presscenter/news/20201207-10587.html

Currently, Samsung Electronics is far behind TSMC's foundry market share in terms of sales. TSMC alone is eating 55.6% of the foundry market, which can be said to be'TSMC and the rest'. Looking at this number alone, there is a very difficult road for Samsung Electronics to overtake TSMC and become number one. Samsung Electronics aims to become'#1 in system semiconductors', and I think that image sensors are possible, but it seems very difficult to beat TSMC with total foundry sales within 10 years.

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However, Samsung does not initially intend to beat TSMC with total sales. If that was the purpose, Samsung's strategy would have been quite different. For example, by acquiring Global Foundry, you can increase your market share by 7% at once. Mubadala, a sovereign wealth fund in Abu Dhabi, owns 100% of the Global Foundry, and continues to sell fabs, and is considering IPOs in 2022. Since it is still owned by Abu Dhabi and is initially licensed for Samsung technology for GlobalFoundry's 14/12nm process, there is no reason for the US government to disallow the acquisition due to concerns about technology leakage.

 

In the graph on the left, you can see TSMC's microprocessing technology nodes and sales ratio. Already, 5nm sales account for 20%. Almost all of them are Apple. 7nm is 29%, and AMD is most likely. However, it should be noted that older processes of 16nm and above account for more than 50% of TSMC's sales, and in particular, older processes of 110-180nm account for 10% of sales. In the 5nm era, I would like to say what 180nm (0.18um) is, but in fact, many semiconductors do not require state-of-the-art processing. The microcontroller that goes into the air conditioner or microwave doesn't have to be an ultra-high-performance CPU made with a 5nm process. So there is always a demand for these things, and TSMC is making significant sales in this market as well. (Although DB HiTek has a market share of less than 1%, it is the driving force that can be ranked in the top 10 in the foundry anyway. This is a foundry that specializes in 200mm wafers and old processes (90-350nm). I'm doing it.)

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However, Samsung Electronics has no intention of eating this red ocean market anyway. Chinese SMIC and UMC are using their flags to enter 14nm, and there are quite a lot of companies above 40nm, and more and more above 90nm, but they are not willing to enter this market except for the old processes that have already been set up in Austin fabs and so on. Conversely, TSMC is the only competitor in the ultra-fine process. Global Foundry initially abandoned the development of processes below 14/12nm (this is also a Samsung technology license), and SMIC and others will take some time to enter 7nm. Intel, which has been the strongest on the planet for many years, has only recently settled on the 10nm process, but this corresponds to the 7nm process of TSMC and Samsung, so it is once again 1 generation behind the TSMC and Samsung Electronics, which are mass-producing 5nm. Even if Intel succeeds in mass production of 7nm in 2023, TSMC and Samsung at that point (assuming that it will succeed) reach 3nm, so they are falling behind again. However, even if Intel follows well, since Intel doesn't intend to run a foundry business (I kept trying, but it broke every time), in the end, Samsung Electronics' only adversary is TSMC.

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So what matters to Samsung is whether it can win the competition between TSMC and cutting-edge microprocessing, not the market share itself. Whether TSMC and Samsung Electronics alone can chase after or surpass TSMC in the post-7nm market in which the space war is fought alone is the problem that separates the fortunes of the Samsung Electronics foundry. This is because the foundry market will eventually be dominated by ultra-fine processing.

https://www.counterpointresearch.com/foundry-industry-revenue-growth-continue-2021/

Samsung has been following TSMC so well. In mass production of 5nm, TSMC was several months earlier, and TSMC's process for 5nm is evaluated to be half that of Samsung's, but Samsung also acquired a share to compete with TSMC by supplying Exynos 2100 and Snapdragon 888. . In the graph above, MediaTek and AMD will go to TSMC and nVIDIA will go to, but anyway, looking at 5nm where actual products are currently being mass-produced, the market share gap between Samsung + Qualcomm (Samsung) and Apple (TSMC) is 1.8 times, which is currently TSMC vs. Samsung. It is much less than the overall share gap of 3 times. ​

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However, even after 5nm, the next generation, such as 3nm, 2nm, 1.4nm, etc. will continue to appear, and at this time, with a very high probability, Samsung Electronics will only be fighting TSMC. Leading fablesses such as Apple, Qualcomm, nVIDIA, and AMD will constantly want state-of-the-art processes. So, over time, the sales graph by process will naturally push the old process. If 5nm is eating 20% ​​right now, 3nm will eat 20% by next year, and 2nm will eat 20% after 3-4 years. Then, at that time, even 5nm will already be a'old process'.

 

For example, in 2020, TSMC's sales ratio is 20% at 5nm and 29% at 7nm. When 3nm comes out in 2022, it eats 20%, and if 5nm eats 30%, this is already 50%. Going to 2024, if 2nm is 20%, 3nm is 30%, and 5nm is 10%, then ultra-fine processes under 5nm will be 60% of TSMC's total sales. It's a rough number, and may actually be higher. What this means is that the proportion of old processes in TSMC's sales will gradually decrease. However, the difference in market share between the two in the ultra-fine process is definitely less than when the old process was included. So the gap between the two shares naturally narrows.

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And 7nm is trying hard to see what SMIC will do, but it will take a long time to produce meaningful quantities, and from 5nm, which requires EUV, we will eat only TSMC and Samsung Electronics anyway. Eventually, as it is today, even more, TSMC and Samsung take over the vast majority of foundry sales. In conclusion, the influence of Samsung Electronics will naturally increase with microprocessing, and that is why Samsung Electronics focuses on ultra-fine process development and mass production rather than expanding the old process capacity.

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2. GAAFET: Will Samsung succeed?

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And in the race for ultra-fine process development, Samsung Electronics has a tremendous number. At 3nm, TSMC continues to adhere to the existing FinFET technology, but Samsung Electronics uses the state-of-the-art Horizontal NanoSheet (HNS)-based Gate-All-Around FET (GAAFET).

First of all, if I describe FET (field-effect transistor) in a very simple way (in the case of NMOS), electrons move freely from'source' to'drain', but when negative voltage is applied to the'gate', the source An energy barrier is created in the'channel' between the and drain, preventing electrons from moving. This is to control the movement of electrons, that is, the flow of current, so this is called a'semiconductor'. A metal-like conductor is a material through which electric current easily flows, and a rubber-like nonconductor is a material in which electric current cannot flow easily, and a'semiconductor' flows or does not change depending on certain conditions.

https://www.samsungsemiconstory.com/1353

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How fast you can control the movement of this current, that is, how fast you can turn the ON/OFF switch off and on, will determine the performance of the transistor. The way to simplify this was to shorten the length of the gate. This is "fine fairness". Then, the size of the transistor is also reduced, so you can fit more transistors in the same area. In many ways, microprocessing has brought great benefits. However, as this length was reduced a lot, there was a problem. Since we applied-voltage to the gate, electrons are blocked by the barrier and cannot move, but because the gate is too short, the electrons cross the wall. This is because of the'quantum tunneling effect' that'there is a probability that electrons will cross the wall'. This leakage current leads to high power consumption and heat generation.

 

FinFET has emerged to solve this problem. It was first commercialized by Intel. Traditionally, if the channel between the source and the drain was buried flat under the gate and touched only one side, FinFET would wrap the raised source and drain on three sides. It is called'FinFET' because it is like a fin when viewed from the side. Since the gate covers the channel with a larger surface area, the flow of current can be more strongly controlled, thus suppressing leakage current. In addition, since the gate can be controlled with a lower voltage, power consumption is reduced, and the actual channel width increases, thus increasing the amount of current that can flow at one time.

 

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The GAAFET takes one more tuft in the FinFET, dividing the fin into layers so that the gate covers all four sides of the channel. That's why it is a'GAA(Gate-All-Around)' FET. When the existing thin pin is made of GAA, it becomes a string and is also called'nanowire'. The problem is that the current control will be much more powerful this way, but the actual channel width is smaller than that of a FinFET, reducing the amount of current that can flow at one time. So, instead of nanowires, the'nano sheet' made in the form of a thin plate by widening the width of the channel attracted attention. This is because the actual channel width can be secured wider than FinFET. HNS stacking these nanosheets horizontally is the way Samsung implements GAAFET. In this way, current control is weaker than nanowires, but better than FinFETs, and the amount of current is more than FinFETs. It's a method with appropriate characteristics in many ways.

With this HNS GAAFET, Samsung intends to increase the density by implementing a 3nm process, significantly reduce power consumption, and significantly increase performance. According to Samsung's claims, performance is reduced by 35% and power consumption is reduced by 50%, while the area is reduced by as much as 45%.

However, TSMC insists that it will increase the density by a whopping 70% at 3nm compared to 5nm. It was 1.8 times when going from 7nm to 5nm, but it's hard to believe whether it is actually setting such an aggressive target at 3nm, but TSMC is so scary that it is highly likely to actually do it. Then, the difference in density at 3nm between Samsung Electronics and TSMC is still significant at 1.5 times. However, in terms of power consumption and performance, not density, there is a possibility that Samsung's 3nm GAAFET will outperform. For example, in the case of performance (assuming that both companies' 7nm are similar), Samsung claims 10% of the improvement in 7nm->5nm and 35% in 5nm->3nm, so a total of 48.5%, TSMC's 7nm->5nm Is 15% and 5nm->3nm is also 15%, so a total of 32.3%. Power consumption is also reduced by 60% for Samsung and 51% for TSMC.

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So, in the case of 5nm, I think TSMC is one level higher than Samsung, but in 3nm, the characteristics of each other are markedly different, so it is difficult to conclude which one is the superior. The density is certainly higher in TSMC, but Samsung could be better in terms of performance and power consumption. Of course, it is only based on the arguments of both companies, and we only know when the actual product comes out. HNS GAAFET may have worse characteristics than you think. It is also the key to success in mass production in time.

 

So, whether Samsung's introduction of 3nm GAAFET will be a trial of the bitter experience in which it first jumped into EUV from 7nm and then entered the market later than TSMC, which implemented 7nm with the existing DUV, or TSMC is clearly a test of performance and power consumption It's a gambling choice where you don't know if it will give you a foothold to jump. TSMC seemed to have made a safe choice to take the existing FinFET one more generation, but at the same time made a very bold choice to increase the density by 1.7 times. Also, we don't know whether to hit the player, or whether it will be reversed by Samsung because it failed mass production at the right time due to the wrong choice like Intel's 10nm. From 3nm, it will be a real space war.

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3. Samsung Electronics' EUV preparation is less than TSMC's?

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The only company in the world that makes EUV exposure machines is ASML in the Netherlands. Thanks to the rivalry between TSMC and Samsung Electronics, selling hundreds of billions of things a year for dozens of things a year is a waste of money. What is often pointed out in this process is that Samsung's EUV exposure machine is less secure than TSMC. According to the Chosun Ilbo article, for example, TSMC has 70 units and Samsung Electronics has 28 units as of next year. If this is substituted for the market share as it is, the share gap will widen. It is not at the level of competition to some extent like today's 5nm, but TSMC will have a clear advantage. But I don't see this as meaning the ultimate defeat of Samsung Electronics. Looking at the Hope Circuit diligently, Samsung may be waiting for the next generation EUV exposure.

 

What is essential for microprocessing is the resolution of the exposure machine. For example, it is a numerical representation of how close two lines can be drawn without overlapping. It's been a while since nanometers are far from the actual gate length, but it's still true that finer patterns need to be drawn as they become finer. The problem is, this in itself is really difficult. This was particularly problematic in DUV, where the wavelength of the light source (193 nm) was much longer than the spacing between the patterns. As an analogy, you have to draw a thin line with a thick brush. So, in DUV, I used a method of increasing the resolution by increasing the numerical aperture (NA), that is, the area where the light exits through water immersion.

 

By exposure, patterning, shaving, covering the spacer, shaving, and then covering the spacer a second time, and then shaving, you can create a pattern that is four times denser than the first pattern. If you want double patterning, you only need to do this process once. But there is a very obvious problem here. The process is too complicated. And the second problem is that even if you use all sorts of technologies such as SAQP for ArF immersion, you eventually run into physical limitations. As TSMC did with SAQP at 7nm, EUV was absolutely necessary at 5nm. Since EUV has a wavelength of 13.5nm, the fundamental resolution is much higher, so the need for quad patterning in DUV can be solved with a single patterning shot. EUV itself has several problems, but at the 5nm level anyway, the problem of resolution seemed to be over.

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The problem is that once microprocessing progresses, EUV single patterning will eventually be insufficient.

I don't know when it will be. It seems that single patterning is used up to 5nm, and 3nm seems to be trying to implement single patterning somehow. It looks like TSMC is pushing it to its de facto limits. However, it doesn't seem to be from 2nm. From this point on, multi-patterning is necessary, but the problem is that multi-patterning in EUV is very difficult and expensive. In particular, if you have to do two exposures, you can make one semiconductor, but because you have to go through two exposure machines, you waste a very expensive and hard-to-find exposure machine. The production will more than double. If EUV double patterning is applied, it is very likely that exposure with SADP will be performed only once. 

https://www.olympus-lifescience.com/ko/microscope-resource/primer/anatomy/numaperture/

 

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Another way to avoid multi-patterning is to increase the resolution by increasing the numerical aperture (NA) of the lens. In short, the larger the area through which light passes, the greater the angle at which the light is drawn with the object, which increases the resolution. In the days of ArF, if NA was increased by increasing the refractive index through liquid immersion, in EUV, optical systems such as mirrors themselves are made much larger. So, it would be natural for the equipment to be more expensive. We did not just increase the size, we put a lot of effort into improving the material and increasing the resolution by drilling holes in the mirror. ASML is testing the EXE:5000, a high-aperture exposure machine with NA=0.55, which is much higher than the current NA=0.33, and according to the roadmap, it is said to start mass production from next year. In order to actually come out, 2023 will have to pass.

 

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So I don't think there is a big problem if Samsung is pushed by TSMC in the competition for securing current-generation EUV exposure machines such as NXE:3400B and 3400C right now. Anyway, EUV foundry competition is a long battle, and I believe that preoccupying next-generation High-NA exposure machines such as EXE:5000 is much more important to Samsung Electronics. No matter how much NXE:3400C is prepared now, it cannot be used in the 1nm generation. Therefore, both Samsung and TSMC will be working really hard with ASML. From the standpoint of ASML, which has become a super-ultra autumn like this, it is natural to sell it to a place that pays more and buys more, but it is also a burden to drive the quantity to one company. Samsung is not only a logic company, but also the world's number one in DRAM and NAND, and Samsung also uses EUV in DRAM.

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So, I think TSMC and Samsung will take the same amount at the time of the high-NA EUV exposure machine on the market. In that case, the confrontation between TSMC and Samsung becomes more important than the external factor of the possibility of a CAPA bottleneck due to securing an ASML exposure machine, but how well they can mass-produce with good technology in the end. Since we have similar production equipment, the theoretical quantity that can be drawn is similar. (Of course, it is necessary to develop and secure other equipment and materials besides the core exposure machine.) If this is the case, Samsung will implement HNS GAAFET, or the next CFET, faster than TSMC and produce more, thereby producing TSMC someday. You can dream of breaking, something that doesn't make sense right now. In the end, they should do well. TSMC is not a quiet place, but rather a preemptive place. Samsung will be a little suffocated if it's not doing anything because it's complacent like Intel, but I never let it go.

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Samsung's goal is to become the #1 system semiconductor by 2030. I'm not sure if it's actually possible. TSMC seems to be a company that works well after 9 years. But looking differently, there are nine years left. In the meantime, technology will continue to develop remarkably, so the process now, the capacity now, will not have much meaning after 9 years. Rather than the next-generation exposure machine that will be released around 2028, the specifications are too different from EXE:5000, the next-generation High-NA exposure machine right now. It's still in the development stage, so many problems will have to be solved, and it won't be coming out on time. For a while, TSMC, which has a lot of 3400Cs, may overwhelm Samsung in terms of capacity. However, Samsung is not trying to beat TSMC right now anyway. If you harden your skills and secure enough next-generation equipment, the possibility of a reversal is open. It all depends on how well Samsung and TSMC are doing. Customers will run first to mass-producing cutting-edge technology first. Which of the two will win. It's a really exciting showdown in the long run.

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